Field of the Invention
Embodiments of the present invention relate generally to graphics processing and, more specifically, to rendering to multi-resolution hierarchies.
Description of the Related Art
A typical computer system includes a central processing unit (CPU) and a graphics processing unit (GPU). Some GPUs are capable of very high performance using a relatively large number of small, parallel execution threads on dedicated programmable hardware processing units. The specialized design of such GPUs usually allows these GPUs to perform certain tasks, such as rendering 3-D scenes, much faster than a CPU. However, the specialized design of these GPUs also limits the types of tasks that the GPU can perform. By contrast, the CPU is typically a more general-purpose processing unit and therefore can perform most tasks. Consequently, the CPU usually executes the overall structure of a software application and then configures the GPU to implement a graphics processing pipeline that transform 3-D images generated by the software application into rendered 2-D images.
For some classes of graphics algorithms it is desirable to render to a multi-resolution representation of a surface, such as mipmaps and multi-resolution shadowmaps. For instance, mipmaps enable an appropriate level of detail to be selected when transforming a 3-D image into a rendered 2-D image, thereby optimizing rendering speed and reducing aliasing artifacts. In operation, after a raster operations unit renders to a multi-resolution representation of a surface, a texture unit accesses the rendered surface to perform texturing operations. In general, the texture unit is configured to access hierarchical surfaces that have blocks of memory laid out in pitch order for each level of the hierarchy. In contrast, the ROP unit is configured to process and store hierarchical surfaces in the same manner in which the ROP unit processes non-hierarchical surfaces. In particular, the ROP unit stores surfaces with blocks in pitch order irrespective of the level of the hierarchy. Consequently, if the ROP unit was to process and store processed graphics data associated with multiple levels of the multi-resolution representation in a single surface, then the texture unit could incorrectly interpret the processed graphics data.
In one approach to ensuring that the processed graphics data in multi-resolution hierarchies is communicated correctly, the software application configures the graphics processing pipeline to render to each hierarchical level separately. As part of the configuration process for each hierarchical level, the software application sets the state parameters describing the render target to reflect the size of the hierarchical level. Further, as part of rendering to each hierarchical level, processing units included in the graphics processing pipeline process each graphics primitive.
For example, suppose that a software application were to configure the computer system to render to a two level mipmap chain. In such as scenario, the software application would set the state parameters describing the render target to reflect the size of the first level in the mipmap chain. The software application would then direct the graphics processing pipeline to render to the first level of the mipmap chain. Subsequently, the software application would set the state parameters describing the render target to reflect the size of the second level in the mipmap chain. The software application would then direct the graphics processing pipeline to render to the second level of the mipmap chain.
One drawback to the above approach is that the state parameter changes are executed by the CPU, not by the GPU in which the graphics processing pipeline is implemented. Consequently, for each change in resolution, the CPU is called upon to effect the necessary state parameter changes. As a general matter, the more times the CPU is called on during rendering, the more overall system performance is compromised. The overall system performance is further comprised because the software application renders to each hierarchical level separately. In particular, the processing results of certain units within the graphics processing pipeline, such as the tessellation processing unit and the vertex processing unit, do not typically vary with the size of the render target. However, since the above approach renders each hierarchical level separately, the tessellation processing unit and the vertex processing unit are re-executed for each hierarchical level. Consequently, these units recompute the same processing results for each hierarchical level.
Accordingly, what is needed in the art is a more effective technique to render to multi-resolution hierarchies.